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november 2004 copyright ? alliance semiconductor. all rights reserved. ? AS7C33256NTD32A as7c33256ntd36a 11/30/04, v. 2.1 alliance semiconductor p. 1 of 19 3.3v 256k32/36 pipelined burst synchronous sram with ntd tm features ? organization: 262,144 words 32 or 36 bits ?ntd ? architecture for efficient bus operation ? fast clock speeds to 166 mhz ? fast clock to data access: 3.5/4.0 ns ?fast oe access time: 3.5/4.0 ns ? fully synchronous operation ? common data inputs and data outputs ? asynchronous output enable control ? available in 100-pin tqfp ? byte write enables ? clock enable for operation hold ? multiple chip enable s for easy expansion ? 3.3 core power supply ? 2.5v or 3.3v i/o operation with separate v ddq ? self-timed write cycles ? interleaved or linear burst modes ? snooze mode for standby operation logic block diagram selection guide -166 -133 units minimum cycle time 6 7.5 ns maximum clock frequency 166 133 mhz maximum clock access time 3.5 4 ns maximum operating current 475 400 ma maximum standby current 130 100 ma maximum cmos standby current (dc) 30 30 ma write buffer address d q clk register output register dq[a:d] 36/32 36/32 18 18 clk ce0 ce1 ce2 a[17:0] oe clk cen control clk logic data d q clk input register 36/32 36/32 36/32 oe 256k x 32/36 sram array r/w dq [a:d] bwa bwc bwb bwd clk q d adv / ld lbo burst logic addr. registers write delay 36/32 18 zz clk
? AS7C33256NTD32A as7c33256ntd36a 11/30/04, v. 2.1 alliance semiconductor p. 2 of 19 8 mb synchronous sram products list 1,2 1 core power supply: vdd = 3.3v + 0.165v 2 i/o supply voltage: vddq = 3.3v + 0.165v for 3.3v i/o vddq = 2.5v + 0.125v for 2.5v i/o pl-scd : pipelined burst synchronous sram - single cycle deselect pl-dcd : pipelined burst synchronous sram - double cycle deselect ft : flow-through burst synchronous sram ntd 1 -pl : pipelined burst synchronous sram with ntd tm ntd-ft : flow-through burst s ynchronous sram with ntd tm org part number mode speed 512kx18 as7c33512pfs18a pl-scd 166/133 mhz 256kx32 as7c33256pfs32a pl-scd 166/133 mhz 256kx36 as7c33256pfs36a pl-scd 166/133 mhz 512kx18 as7c33512pfd18a pl-dcd 166/133 mhz 256kx32 as7c33 256 pfd32a pl-dcd 166/133 mhz 256kx36 as7c33 256 pfd36a pl-dcd 166/133 mhz 512kx18 as7c33512ft18a ft 7.5/8.5/10 ns 256kx32 as7c33 256 ft32a ft 7.5/8.5/10 ns 256kx36 as7c33 256 ft36a ft 7.5/8.5/10 ns 512kx18 as7c33512ntd18a ntd-pl 166/133 mhz 256kx32 as7c33 256 ntd32a ntd-pl 166/133 mhz 256kx36 as7c33 256 ntd36a ntd-pl 166/133 mhz 512kx18 as7c33512ntf18a ntd-ft 7.5/8.5/10 ns 256kx32 as7c33 256 ntf32a ntd-ft 7.5/8.5/10 ns 256kx36 as7c33 256 ntf36a ntd-ft 7.5/8.5/10 ns 1. ntd: no turnaround delay. ntd tm is a trademark of alliance semiconducto r corporation. all trademarks mentione d in this document are the property of their respective owners.
? AS7C33256NTD32A as7c33256ntd36a 11/30/04, v. 2.1 alliance semiconductor p. 3 of 19 pin arrangement for tqfp (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 lbo a a a a a1 a0 nc nc v ss v dd nc nc a a a a a a 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a ce0 ce1 bwd bwc bwb bwa ce2 v dd v ss clk r/w cen oe adv/ld nc a a a tqfp 14x20mm a dqpc/nc dqc0 dqc1 v ddq v ssq dqc2 dqc3 dqc4 dqc5 v ssq v ddq dqc6 dqc7 nc v dd nc v ss dqd0 dqd1 v ddq v ssq dqd2 dqd3 dqd4 dqd5 v ssq v ddq dqd6 dqd7 dqpd/nc dqpb/nc dqb7 dqb6 v ddq v ssq dqb5 dqb4 dqb3 dqb2 v ssq v ddq dqb1 dqb0 v ss zz dqa7 dqa6 v ddq v ssq dqa5 dqa4 dqa3 dqa2 v ssq v ddq dqa1 dqa0 dqp/nc v dd nc note: pins 1, 30, 51 , and 80 are nc for 32
? AS7C33256NTD32A as7c33256ntd36a 11/30/04, v. 2.1 alliance semiconductor p. 4 of 19 functional description the as7c33256ntd32/36a family is a high performance cmos 8 mbit synchronous static random acce ss memory (sram) organized as 262,144 words 32 or 36 bits a nd incorporates a late late write. this variation of the 8mb sychronous sram uses the no turnaround delay (ntd ? ) architecture, featuring an enhanced write operation that improves bandwidth over pipelined burst devices. in a normal pipelined burst devi ce, the write data, co mmand, and address are all applied to the device on the same clock edge . if a read command follows this write command, the system must wait for two 'dead' cycles for valid data to become available. these de ad cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write operations. ntd ? devices use the memory bus more efficien tly by introducing a write latency which matc hes the two-cycle pipelined or one-cycle flow-through read latency. write data is a pplied two cycles after the wr ite command and address, allo wing the read pipeline to clear. with ntd ? , write and read operations can be used in any order without produci ng dead bus cycles. assert r/w low to perform write cycles. byte write enable controls write access to specific bytes, or can be tied low for full 32/36 bit writes. write enable signals, along with th e write address, are registered on a rising edge of the clock. write data is applied to the device two clock cycles later. unlike some asyn chronous srams, output enable oe does not need to be toggled for write operations; it can be tied low for normal operations. outputs go to a high impedance state when the de vice is de-selected by any of the three chip enable inputs. in pipelined mode, a two cycle deselect late ncy allows pending read or wr ite operations to be completed. use the adv (burst advance) input to perform burst read, writ e and deselect operati ons. when adv is high, external addresses, chip select, r/w pins are ignored, and internal address counters in crement in the count sequence specified by the lbo control. any de vice operations, including burst, can be stalled using the cen =1, the clock enable input. the as7c33256ntd36a and AS7C33256NTD32A operate with a 3.3v 5% power supply for the device core (v dd ). dq circuits use a separate power supply (v ddq ) that operates across 3.3v or 2.5v ranges. these devices are availabl e in a 100-pin 1420 mm tqfp package * guaranteed not tested tqfp thermal resistance capacitance parameter symbol test conditions min max unit input capacitance c in * v in = 0v - 5 pf i/o capacitance c i/o * v in = v out = 0v - 7 pf description conditions symbol typical units thermal resistance (junction to ambient) 1 1 this parameter is sampled test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51 1?layer ja 40 c/w 4?layer ja 22 c/w thermal resistance (junction to top of case) 1 jc 8 c/w
? AS7C33256NTD32A as7c33256ntd36a 11/30/04, v. 2.1 alliance semiconductor p. 5 of 19 snooze mode snooze mode is a low current, power-down mode in whic h the device is deselected and current is reduced to i sb2 . the duration of snooze mode is dictated by th e length of time the zz is in a high state. the zz pin is an asynchronous, active high input that causes the device to enter snooze mode. when the zz pin becomes a logic high, i sb2 is guaranteed after the time t zzi is met. after entering snooze mode, all inputs except zz is disabled and all outputs go to high-z. any oper ation pending when entering snooze mode is not guaranteed to successfully complete. therefore, sn ooze mode (read or write) must not be initiated until va lid pending operations are completed. similarly, when exiting snooze mode during t pus , only a deselect or read cycle should be given while the sram is transitioning out of snooze mode. signal descriptions signal i/o properties description clk i clock clock. all inputs except oe , lbo , and zz are synchronous to this clock. cen i sync clock enable. when de-asserted high , the clock input signal is masked. a, a0, a1 i sync address. sampled when all chip enables are active and adv/ld is asserted. dq[a,b,c,d] i/o sync data. driven as outp ut when the chip is enabled and oe is active. ce0 , ce1, ce2 i sync synchronous chip enables. sampled at the rising edge of clk, when adv/ld is asserted. are ignored when adv/ld is high. adv/ld i sync advance or load. when sampled high, the internal burst address counter will increment in the order defined by the lbo input value. (refer to table on page 2) when low, a new address is loaded. r/w i sync a high during load initiates a read oper ation. a low during load initiates a write operation. is ignored when adv/ld is high. bw[a,b,c,d] i sync byte write enables. used to control write on individual bytes. sampled along with write command and burst write. oe i async asynchronous output enable. i/o pins are not driven when oe is inactive. lbo istatic selects burst mode. when tied to v dd or left floating, device follows interleaved burst order. when driven low, device follows linear burst order. this signal is internally pulled high. zz i async snooze. places device in low power mode; data is retain ed. connect to gnd if unused. nc - - no connect. note that pin 84 will be used for future address expansion to 16mb density.
? AS7C33256NTD32A as7c33256ntd36a 11/30/04, v. 2.1 alliance semiconductor p. 6 of 19 synchronous truth table [5,6,7,8,9 ] key : x = don?t care, h = high, l = low. bw n = h means all byte write signals (bw a, bw b, bw c, and bw d) are high. bw n = l means one or more byte write signals are low. notes: 1 continue burst cycles, whether read or write, use the same cont rol inputs. the type of cycle performed (read or write) is cho se in the initial begin burst cycle. a coninue deselect cycle can only be entered if a deselect cycle is executed first. 2 dummy read and write abort cycles can be c onsidered nops because the device performs no external operation. a write abort mea ns a write command is given, but no operation is performed. 3 oe may be wired low to minimize the number of control signal to the sram. the device w ill automatically turn off the output drive rs during a write cycle. oe may be used when the bus turn-on and turn-off times do not meet an ap plication?s requirements. 4 if an inhibit clock command o ccurs during a read operation, the dq bus will re main active (low-z). if it occurs during a wri te cycle, the bus will remain in high-z. no write operations will be performed during the inhibit clock cycle. 5 bw a enables writes to byte ?a? (dqa pins/balls); bw b enables writes to byte ?b? (dqb pins/balls); bw c enables writes to byte ?c? (dqc pins/ balls); bw d enables writes to byte ?d? (dqd pins/balls). 6 all inputs except oe and zz must meet setup and hold times around the rising edge (low to high) of clk. 7 wait states are inserted by setting cen high. 8 this device contains circuitry that will ensure that the outputs will be in high-z during power-up. 9 the device incorporates a 2-bit burst counter. address wraps to the initia l address every fourth burst cycle. 10 the address counter is incremen ted for all continue burst cycles. 11 zz pin is always low in this truth table. burst order interleaved burst order (lbo =1) linear burst order (lbo =0) a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 starting address 0 0 0 1 1 0 1 1 starting address 0 0 0 1 1 0 1 1 first increment 0 1 0 0 1 1 1 0 first increment 0 1 1 0 1 1 0 0 second increment 1 0 1 1 0 0 0 1 second increment 1 0 1 1 0 0 0 1 third increment 1 1 1 0 0 1 0 0 third increment 1 1 0 0 0 1 1 0 ce0 ce1 ce2 adv/ld r/w bw n oe cen address source clk operation dq notes h x x l x x x l na l to h deselect cycle high-z x x h l x x x l na l to h deselect cycle high-z x l x l x x x l na l to h deselect cycle high-z x x x h x x x l na l to h continue deselect cycle high-z 1 l h l l h x l l external l to h read cycle (begin burst) q x x x h x x l l next l to h read cycle (continue burst) q 1,10 l h l l h x h l external l to h nop/dummy read (begin burst) high-z 2 x x x h x x h l next l to h dummy read (continue burst) high-z 1,2,10 l h l l l l x l external l to h write cycle (begin burst) d 3 x x x h x l x l next l to h write cycle (continue burst) d 1,3,10 l h l l l h x l external l to h nop/write abort (begin burst) high-z 2,3 x x x h x h x l next l to h write abort (continue burst) high-z 1,2,3, 10 x x x x x x x h current l to h inhibit clock - 4
? AS7C33256NTD32A as7c33256ntd36a 11/30/04, v. 2.1 alliance semiconductor p. 7 of 19 state diagram for ntd sram recommended operating conditions at 3.3v i/o recommended operating conditions at 2.5v i/o absolute maximum ratings 1 1 stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions may affect reliability. parameter symbol min max unit power supply voltage relative to gnd v dd , v ddq ?0.5 +4.6 v input voltage relative to gnd (input pins) v in ?0.5 v dd + 0.5 v input voltage relative to gnd (i/o pins) v in ?0.5 v ddq + 0.5 v power dissipation p d ?1.8w dc output current i out ?50ma storage temperature (plastic) t stg ?65 +150 o c temperature under bias (junction) t bias ?65 +150 o c parameter symbol min nominal max unit supply voltage for inputs v dd 3.135 3.3 3.465 v supply voltage for i/o v ddq 3.135 3.3 3.465 v ground supply vss 0 0 0 v parameter symbol min nominal max unit supply voltage for inputs v dd 3.135 3.3 3.465 v supply voltage for i/o v ddq 2.375 2.5 2.625 v ground supply vss 0 0 0 v dsel dsel r ead read burst burst write read write burst read read write d s e l r e a d burst write dsel d s e l w r i t e w r i te burst dsel burst burst write read
? AS7C33256NTD32A as7c33256ntd36a 11/30/04, v. 2.1 alliance semiconductor p. 8 of 19 dc electrical characterist ics for 3.3v i/o operation dc electrical characteristics for 2.5v i/o operation * v ih max < vdd +1.5v for pulse width less than 0.2 x t cyc ** v il min = -1.5 for pulse wi dth less than 0.2 x t cyc i dd operating conditions and maximum limits parameter sym conditions min max unit input leakage current 1 1 lbo , and zz pins have an internal pull-up or pull-down, and input leakage = 10 a. |i li |v dd = max, 0v < v in < v dd -2 2 a output leakage current |i lo |oe v ih , v dd = max, 0v < v out < v ddq -2 2 a input high (logic 1) voltage v ih address and control pins 2 * v dd +0.3 v i/o pins 2 * v ddq +0.3 input low (logic 0) voltage v il address and control pins -0.3 ** 0.8 v i/o pins -0.5 ** 0.8 output high voltage v oh i oh = ?4 ma, v ddq = 3.135v 2.4 ? v output low voltage v ol i ol = 8 ma, v ddq = 3.465v ? 0.4 v parameter sym conditions min max unit input leakage current |i li |v dd = max, 0v < v in < v dd -2 2 a output leakage current |i lo |oe v ih , v dd = max, 0v < v out < v ddq -2 2 a input high (logic 1) voltage v ih address and control pins 1.7 * v dd +0.3 v i/o pins 1.7 * v ddq +0.3 v input low (logic 0) voltage v il address and control pins -0.3 ** 0.7 v i/o pins -0.3 ** 0.7 v output high voltage v oh i oh = ?4 ma, v ddq = 2.375v 1.7 ? v output low voltage v ol i ol = 8 ma, v ddq = 2.625v ? 0.7 v parameter sym test conditions -166 -133 unit operating power supply current 1 1 i cc given with no output loading. i cc increases with faster cycle times and greater output loading. i cc ce0 < v il , ce1 > v ih , ce2 < v il , f = f max , i out = 0 ma, zz < v il 475 400 ma standby power supply current i sb all v in 0.2v or > v dd ? 0.2v, deselected, f = f max , zz < v il 130 100 ma i sb1 deselected, f = 0, zz < 0.2v, all v in 0.2v or v dd ? 0.2v 30 30 i sb2 deselected, f = f max , zz v dd ? 0.2v, all v in v il or v ih 30 30
? AS7C33256NTD32A as7c33256ntd36a 11/30/04, v. 2.1 alliance semiconductor p. 9 of 19 timing characteristics for 3.3 v i/o operation parameter symbol ?166 ?133 unit notes 1 1 refer to ?notes? on page 16. min max min max clock frequency f max ? 166 ? 133 mhz cycle time t cyc 6?7.5? ns clock access time t cd ?3.5?4.0 ns output enable low to data valid t oe ?3.5?4.0 ns clock high to output low z t lzc 0 ? 0 ? ns 2,3,4 data output invalid from clock high t oh 1.5?1.5? ns 2 output enable low to output low z t lzoe 0 ? 0 ? ns 2,3,4 output enable high to output high z t hzoe ? 3.5 ? 4.0 ns 2,3,4 clock high to output high z t hzc ? 3.5 ? 4.0 ns 2,3,4 output enable high to invalid output t ohoe 0?0? ns clock high pulse width t ch 2.4?2.5? ns 5 clock low pulse width t cl 2.3?2.5? ns 5 address and control setup to clock high t as 1.5?1.5? ns 6 data setup to clock high t ds 1.5?1.5? ns 6 write setup to clock high t ws 1.5 ? 1.5 ? ns 6,7 chip select setup to clock high t css 1.5 ? 1.5 ? ns 6,8 address hold from clock high t ah 0.5?0.5? ns 6 data hold from clock high t dh 0.5?0.5? ns 6 write hold from clock high t wh 0.5 ? 0.5 ? ns 6,7 chip select hold from clock high t csh 0.5 ? 0.5 ? ns 6,8 clock enable setup to clock high t cens 1.5?1.5? ns 6 clock enable hold from clock high t cenh 0.5?0.5? ns 6 adv/ld setup to clock high t advs 1.5?1.5? ns 6 adv/ld hold from clock high t advh 0.5?0.5? ns 6
? AS7C33256NTD32A as7c33256ntd36a 11/30/04, v. 2.1 alliance semiconductor p. 10 of 19 snooze mode electric al characteristics timing characteristics for 2.5 v i/o operation parameter symbol ?166 ?133 unit notes 1 min max min max clock frequency f max ? 166 ? 133 mhz cycle time t cyc 6?7.5?ns clock access time t cd ? 3.8 ? 4.2 ns output enable low to data valid t oe ? 3.5 ? 4.0 ns clock high to output low z t lzc 0 ? 0 ? ns 2,3,4 data output invalid from clock high t oh 1.5?1.5? ns 2 output enable low to output low z t lzoe 0 ? 0 ? ns 2,3,4 output enable high to output high z t hzoe ? 3.5 ? 4.0 ns 2,3,4 clock high to output high z t hzc ? 3.5 ? 4.0 ns 2,3,4 output enable high to invalid output t ohoe 0?0?ns clock high pulse width t ch 2.4?2.5? ns 5 clock low pulse width t cl 2.3?2.5? ns 5 address setup to clock high t as 1.7?1.7? ns 6 data setup to clock high t ds 1.7?1.7? ns 6 write setup to clock high t ws 1.7?1.7? ns 6,7 chip select setup to clock high t css 1.7?1.7? ns 6,8 address hold from clock high t ah 0.7?0.7? ns 6 data hold from clock high t dh 0.7?0.7? ns 6 write hold from clock high t wh 0.7?0.7? ns 6,7 chip select hold from clock high t csh 0.7?0.7? ns 6,8 clock enable setup to clock high t cens 1.7?1.7? ns 6 clock enable hold from clock high t cenh 0.7?0.7? ns 6 adv/ld setup to clock high t advs 1.7?1.7? ns 6 adv/ld hold from clock high t advh 0.7?0.7? ns 6 1 refer to ?notes? on page 16. description conditions symbol min max units current during snooze mode zz > v ih i sb2 30 ma zz active to input ignored t pds 2cycle zz inactive to input sampled t pus 2cycle zz active to snooze current t zzi 2cycle zz inactive to exit snooze current t rzzi 0
? AS7C33256NTD32A as7c33256ntd36a 11/30/04, v. 2.1 alliance semiconductor p. 11 of 19 key to switching waveforms timing waveform of read cycle undefined falling input rising input don?t care t ch t cyc t cl t as clk cen r/w t ceh a1 a2 a3 address t ah t ces t ws t wh ce0 ,ce2 t advs t csh dout ce1 t advh t oe t lzoe t hzoe q(a1) q(a2y?01) q(a2) q(a3) t hlzc oe adv/ld bwn t ws t wh q(a2y?10) q(a2y?11) read q(a1) dsel read q(a2) continue read q (a2y?01) continue read q (a2y?10) continue read q (a2y?11) inhibit clock read q(a3) continue read q (a3y?01)
? AS7C33256NTD32A as7c33256ntd36a 11/30/04, v. 2.1 alliance semiconductor p. 12 of 19 timing waveform of write cycle t ch t cyc t cl t as clk cen r/w t ceh a1 a2 a3 address t ah t ces ce0 ,ce2 t advs t csh din ce1 t advh t hzoe d(a1) d(a2) d(a3) t ds oe adv/ld t dh q(n-2) dout bwn q(n-1) d(a2y?01) d(a2y?10) d(a2y?11) write d(a1) dsel write d(a2) continue write d (a2y?01) continue write d (a2y?10) continue write d (a2y?11) inhibit clock write d(a3) continue write d (a3y?01)
? AS7C33256NTD32A as7c33256ntd36a 11/30/04, v. 2.1 alliance semiconductor p. 13 of 19 timing waveform of read/write cycle note: y = xor when lbo = high/no connect. y = add when lbo = low. bw[a:d] is don?t care. t ch t cyc t cl t cens t oh t oe clk cen ce0 , ce2 adv/ld r/w address d/q oe command t hzoe bwn a2 a1 a3 a5 a4 a7 a6 d(a1) d(a5) q(a6) d(a2) d(a2 y 01) q(a3) q(a4) q(a4 y 01 ) t cenh t ds t dh t lzc t cd t hzc t lzoe read q(a3) read q(a4) burst read q(a4y01) write d(a5) read q(a6) write d(a7) dsel t css t advh t ws t wh t ws t wh ce1 write d(a1) write d(a2) t advs t csh t as t ah burst write d(a2y01)
? AS7C33256NTD32A as7c33256ntd36a 11/30/04, v. 2.1 alliance semiconductor p. 14 of 19 nop, stall and deselect cycles note: y = xor when lbo = high/no connect; y = add when lbo = low. oe is low. clk cen ce0 , ce2 adv/ld r/w address d/q command bwn a1 a2 q(a1) d(a2) q(a1 y 01) q(a1 y 10) burst q(a1y01 ) stall dsel burst dsel write d(a2) burst nop d(a2y01 ) write nop d(a3) a3 read q(a1) burst q(a1y10 ) burst d(a2y10) ce1
? AS7C33256NTD32A as7c33256ntd36a 11/30/04, v. 2.1 alliance semiconductor p. 15 of 19 timing waveform of snooze mode ac test conditions clk all inputs zz t zzi i supply (except zz) dout t pus zz recovery cycle i sb2 t rzzi zz setup cycle deselect or read only deselect or read only normal operation cycle high-z z 0 =50 ? d out 50 ? v l =1.5v figure b: output load (a) 30 pf* figure a: input waveform 10% 90% gnd 90% 10% +3.0v ? output load: see figure b, except for t lzc , t lzoe , t hzoe , t hzc see figure c. ? input pulse level: gnd to 3v. see figure a. ? input rise and fall time (m easured at 0.3v and 2.7v): 2 ns. see figure a. ? input and output timing reference levels: 1.5v. 353 ?/ 1538 ? 5 pf* 319 ? /1667 ? d out gnd figure c: output load(b) *including scope and jig capacitance thevenin equivalent: +3.3v for 3.3v i/o; /+2.5v for 2.5v i/o
? AS7C33256NTD32A as7c33256ntd36a 11/30/04, v. 2.1 alliance semiconductor p. 16 of 19 notes 1 for test conditions, see ac test conditions , figures a, b, c. 2 this parameter measured with out put load condition in figure c 3 this parameter is sample d and not 100% tested. 4t hzoe is less than t lzoe ; and t hzc is less than t lzc at any given temper- ature and voltage. 5 t hzcn is a ?no load? parameter to indicate exactly when sram outputs have stopped driving. 6i cc given with no output loading. i cc increases with faster cycle times and greater output loading. 7 transitions are measured 500 mv from steady state voltage. output loading specified with c l = 5 pf as in figure c. 8t ch measured as high above vih, and t cl measured as low below vil 9 this is a synchronous device. all addresses must meet the specified setup and hold times for all rising ed ges of clk. all other synchronous inputs must meet the setup and hold tim es with stable logic levels for all rising edges of clk when chip is enabled.
? AS7C33256NTD32A as7c33256ntd36a 11/30/04, v. 2.1 alliance semiconductor p. 17 of 19 package dimensions he e hd d b e tqfp min max a1 0.05 0.15 a2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 d 13.80 14.20 e 19.80 20.20 e 0.65 nominal hd 15.80 16.20 he 21.80 22.20 l 0.45 0.75 l1 1.00 nominal 0 7 dimensions in millimeters 100-pin quad flat pack (tqfp) a1 a2 l1 l c
? AS7C33256NTD32A as7c33256ntd36a 11/30/04, v. 2.1 alliance semiconductor p. 18 of 19 o rdering information note: add suffix ?n? to he above part numbers fo r lead free parts (ex. AS7C33256NTD32A-166tqcn) part numbering guide 1.alliance semiconductor sram prefix 2.operating voltage: 33 = 3.3v 3.organization: 256 = 256 k 4.ntd tm = no turn-around delay. pipelined mode. 5.organization: 32 = x32; 36 = x36 6.production version: a = first production version 7.clock speed (mhz) 8.package type: tq = tqfp. 9.operating temperature: c = commercial ( 0 c to 70 c); i = industrial ( -40 c to 85 c) 10. n = lead free part package width 166 mhz 133 mhz tqfp 32 AS7C33256NTD32A -166tqc AS7C33256NTD32A -133tqc tqfp 32 AS7C33256NTD32A -166tqi AS7C33256NTD32A -133tqi tqfp 36 as7c33256ntd36a -166tqc as7c33256ntd36a -133tqc tqfp 36 as7c33256ntd36a -166tqi as7c33256ntd36a -133tqi as7c 33 256 ntd 32/36 a ?xxx tq c/i x 1 23 45678 910
AS7C33256NTD32A as7c33256ntd36a ? ? copyright 2003 alliance semiconductor corporation. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves th e right to make changes to th is document and its products at any time without notice. al liance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance's best data and/or esti mates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications are possi ble. the information in this product data sheet is intended to be general descriptive information for potential custom ers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any expr ess or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as ex press agreed to in alliance' s terms and conditions of sale (which are available from alliance). al l sales of alliance products are made exclusively according to alliance's terms and conditions of sale. the purchase of products from al liance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intell ectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life- supporting systems implies that the manufacturer assumes all ri sk of such use and agrees to indemnify alliance against all claims arising from such use. alliance semiconduc tor corporation 2575, augustine drive, santa clara, ca 95054 tel: 408 - 855 - 4900 fax: 408 - 855 - 4999 www.alsc.com copyright ? alliance semiconductor all rights reserved part number:as7c33256ntd36a document version: v. 2.1 ? AS7C33256NTD32A

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